The present invention relates to a method of fabrication of semiconductor integrated circuit devices, and, more particularly, to a technique that is effective when applied to the testing of semiconductor integrated circuit devices, including semiconductor memories.
Various techniques have been proposed with respect to test burn-in systems which evaluate and determine the acceptability of semiconductor integrated circuit devices that constitute devices to be tested in burn-in. An example of such proposals is Japanese Unexamined Patent Publication No. Hei 06 (1994)-283657 (Patent Document 1). As described in Patent Document 1, test burn-in systems are based on batch processing.
There are various test techniques for test burn-in systems. Examples include: Japanese Unexamined Patent Publication No. 2003-57292 (Patent Document 2), Japanese Unexamined Patent Publication No. 2000-40390 (Patent Document 3), and Japanese Unexamined Patent Publication No. Hei 05 (1993)-55328 (Patent Document 4). Patent Document 2 discloses a technique wherein burn-in boards are divided into test groups and signals are supplied on a test group-by-test group basis in burn-in. Patent Document 3 discloses a technique wherein semiconductor integrated circuit devices are divided into a plurality of groups and semiconductor integrated circuit devices are subjected to pass/fail tests on a group-by-group basis. Patent Document 4 discloses a technique wherein, with voltage continuously applied, semiconductor integrated circuit devices are transported in a thermostatic bath and each semiconductor integrated circuit device is subjected to electrical tests at a test station. [Patent Document 1] Japanese Unexamined Patent Publication No. Hei 06(1994)-283657
[Patent Document 2] Japanese Unexamined Patent Publication No. 2003-57292
[Patent Document 3] Japanese Unexamined Patent Publication No. 2000-40390
[Patent Document 4] Japanese Unexamined Patent Publication No. Hei 05(1993)-55328